Authors:
Biswarup Mukherjee,Aniruddha Ghosal,DOI NO:
https://doi.org/10.26782/jmcms.2018.08.00009Keywords:
Half-band FIR filter,Dual Edge Triggered Flip Flop (DETFF), GDI ,Multiplexer, Low power VLSI ,Abstract
In this paper, a technique for implementing low-power equiripple half-band FIR filter using GDI based Dual Edge Triggered Flip Flop (DETFF) is introduced. Dual edge triggered flip flops has many advantages in low power VLSI compared to SETFF. The Proposed low power FIR filter using DETFF is implemented and compared with conventional design at same simulation conditions. CAD tool based simulation and comparison between proposed design with the conventional design shows that the proposed design reduces power dissipation by 32% reducing the no. of transistors used while keeping the same data rate.Refference:
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Author(s): Biswarup Mukherjee, Aniruddha Ghosal View Download