Authors:
N. Malathi,B. Srinivas,K. Sainath,J. Hemanth Kumar,DOI NO:
https://doi.org/10.26782/jmcms.2019.08.00039Keywords:
Pipe line transaction,lock transaction,single transaction,and burst transaction,SoC,Abstract
System on chip design enables more and more IP core integration to meet demands of era of multimillion gate chips. The new levels of integration present significant challenges to provide compatible STD interfaces and flexible bus architectures. IP cores which are constituents of SOCs are designed with many different interfaces and common protocols. In paper proposing well define standard interface, the open core protocol for a hybrid method of AHB bus based architecture. The hybrid approach of AHB bus architecture defines a set of bus interface to make easy basic and rupture read/write transactions.AHS as well define inner shared bus architecture with multiplexers which can accommodate a small number of IP cores facilitating multi master, multi slave operation s simultaneously. OPC-has been selected since it is release to the public and OCP-IP features cross bar/partial cross bar based inter connect and realizes various techniques. The tradeoffs for using OCP interface with AHB bus architecture are concluded in terms of orthogonality, performance, power and bandwidth. Each memory sub system achieved its maximum bandwidth because of OCP-interface.Refference:
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