Performance analysis of carbon nanotubes forfuture highspeed VLSI on-chip interconnect applications

Authors:

Ch. Praveen Kumar,E. Sreenivasa Rao,P. Chandrasekhar,

DOI NO:

https://doi.org/10.26782/jmcms.2019.08.00041

Keywords:

Carbon nanotube FETs (CNFETs),CMOS,Single walled carbon nantube (SWCNT),Multi walled carbon nanotube (MWCNT),interconnects,

Abstract

In VLSI, while we pass into a sub-micron stage, power dissipation and propagation delay problems occur mainly due to the interconnect parasitic. This motivates the designing of low power interconnects with less propagation delay. This work analyzed the crosstalk induce delay of on-chip interconnects such as copper, SWCNT, and MWCNT with resistive, CMOS and CNTFETdrivers to improve the performance metrics.A two-line driver-interconnect-load (DIL) system is used to analyze the crosstalk induced delay for different interconnect lengths by calculating the equivalent R, L and C parameters of copper and CNT based interconnects. From the simulations, it has been observed that MWCNT interconnects given better performance than conventional copper and SWCNT interconnects when driving through CNTFET driver in terms of power and delay. It is almost given more than 50% lesser delay and power consumption in comparison with others. Additionally, we have performed the crosstalk peak voltage analysis for different interconnect lengths and it is evident that crosstalk can be reduced by changing the coupling and load capacitances. Moreover the MWCNTs have given a 55% lesser noise peaks than the conventional copper interconnects.

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