DESIGN OF HIGH PERFORMANCEADDER USING MODIFIED GDI BASED FULL ADDER

admin August 21, 2020

Authors:

P.Kishore,K.C.Koteswaramma,Y.Chalapathi Rao,

DOI NO:

https://doi.org/10.26782/jmcms.2020.08.00006

Keywords:

1-bit full adder,Carry Save Adder,Gate Diffusion Input,Power Dissipation,Propagation Delay,

Abstract

Adders are the fundamental building blocks for any digital processors in VLSI design. Thepropagation delay should be low for high level applications and thus the speed is depends on the propagation delay of the full adders.Hence, the efficientdesign of the full adder is one of the major concerns in fulfilling the requirements of latest applications. As there is lot of research is carrying on full adder designs, still there is a scope of improvement. This paper aimed at design of high performance Carry Save Adder (CSA) using a modified 1-bit full adder. Initially, the basic building blocki.e., a full adder is discussed using existing and proposed Modified Gate Diffusion Input (Modified GDI) techniques. Later, by using this proposed adder the CSA have been designed and compared its performance with respect to speed, Power dissipation and area. All the proposed designs are designed in mentor graphics tools at 90nm technology.

Refference:

I. Morgenshtein A. Fish, I.A. Wagner. “GateDiffusion Input (GDI) – A Power Efficient Method forDigital Combinational Circuits”, IEEE Transactions on VLSI, Vol.10, No. 5, pp 566-581(2002).

II. Pinninti Kishore, P.V. Sridevi, K. Babulu, “LowPower and Optimized Ripple Carry Adder and CarrySelect Adder Using MOD-GDI Technique”,Proceedings of Microelectronics, Electromagneticsand Telecommunications, Lecture Notes in ElectricalEngineering, Springer India. pp 159-171(2016).

III. Kiat -Seng Yeo, Kaushik Roy, “Low -Voltage,Low- Power VLSI Subsystems” Tata McGraw-HilEdition, pp. 83-85(2009).

IV. T.Kim, W. Jao, S. Tjiang, “Arithmeticoptimization using carry save adders”, Proceedings of Designautomation Conference, pp 433-438(1998).

V. T. Kim, W. Jao, S.Tjiang, “Circuitoptimization using carry saver adder cells”, IEEETransanctions on Computer Aided design of integrated circuitsand systems, Vol. 17, No. 10, pp 974-984(1998).

VI. Pinninti Kishore, P.V. Sridevi, K. Babulu, K.S.Pradeep Chandra, “A Novel Low Power andArea Efficient Carry-Lookahead Adder using Mod-GDI Technique”, International Journal of Scientificand Research, Vol. 4, No. 5, pp 1205-1210(2015).

VII. S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A.Bryant, L. Chang, K. K. Das, W. Haensch, E. J Nowak, D. Sylvester, “Ultralow-voltage,minimum-energy CMOS”, IBM Journal of Researchand Development, Vol. 50, No.5, pp 469-490(2006).

View Download