An Implementation of Area Optimized Low Power MAC

admin June 28, 2019

Authors:

P. Ashok Babu,

DOI NO:

https://doi.org/10.26782/jmcms.2019.06.00009

Keywords:

Digital Signl Processing,MAC,

Abstract

The objective of the paper is to develop an Area optimized Low power digital circuit for MAC (Multiply and Accumulate) operation. We developed implementations of the MAC to avoid using multipliers and prefer to use the combinational circuits like multiplexers. We analyze all the MAC digital circuits to find out the best digital circuit which consumes minimum area and power. MAC is basic building block of many Digital Signal Processing Applications like Noise Cancellation Circuits, Speech Processing, Image Processing, Video Processing, Artificial Neural Networks etc. We also give some suggestions on the system level solutions based on the MAC. The digital circuit which is developed by us will be compatible to FPGAs, as it is developed by the industry standard Synthesis tool i.e. Synopsys Synlipy pro synthesis tool. The MAC which we are developing can be placed in the FPGA Fabric and it can be interfaced to any processors like Cortex M3, Cortex M0, 805 1etc. The overall throughput decreases due high latency and increase in the processing time. So, all the MAC operations must be performed in the hardware by the MAC block developed by us as it is low power, low area and fast hardware.

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P. Ashok Babu View Download