Authors:
Uma Nirmal,V.K. Jain,DOI NO:
https://doi.org/10.26782/jmcms.2018.06.00008Keywords:
2/3 prescaler, 4/5 prescaler, divide by 32/33 prescalers, I –ETSPC,Sleepy Keeper Approach,Abstract
n this paper, we implement divide by 32/33 dual modulus prescaler(DMP) using I-ETSPC based: divide by 2/3prescaler and divide by 4/5 by prescaler at 180nm CMOS technology. The divide by 32/33 dual modulus prescaler using 2/3 prescaler and 4/5 prescaler consumes 1.03mW and 0.85mW power from 1.2V and 1V respectively. To further improve speed and reduce design complexity with low power consumption a pseudo divide by 32/33 dual modulus prescaler is proposed. According to simulation results the pseudo divide by 32/33 dual modulus prescaler reaches a maximum 9.2 GHz working frequency at 1V with a 0.17mw power consumption. This prescaler is compared with Proposed I-ETSPC based divide by 32/33 using 2/3 and 4/5 prescalers and also with other recently published divide by 32/33 prescalers.Compared with previous conventional divide by 32/33 DMPs, this design contains fewer transistor numbers.Refference:
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Author(s): Uma Nirmal, V.K. Jain View Download