Authors:
Muhammad Yousaf Ali Khan,Abid Saleem,Asif Nawaz,Nasru Minallah,Rehan Ali Khan,Muneeb Sadat,Zeeshan Najam,Sheeraz Ahmed,DOI NO:
https://doi.org/10.26782/jmcms.2020.08.00051Keywords:
Array binding and allocation,Dynmic random-access memory (DRAM),effective sheduling,empty slots management,memory latency,multi-core processors on chip (MPSoC).,Abstract
The modern digital systems especially those dealing with enormous data consumption application are facing a very complicated problem of high latency in these memory access application. Latency seems to be a major hurdle in the performance of modern memory dependent systems as it experiences delay in the processing. This high latency depends upon too many factors especially applications involving memory access operation. Out of these major factors one is of the binding and allocation application. Number of different approaches in the recent past has adopted to optimize the high latency in memory access application. Yet the modern embedded system faces high latency still due to enormous data transfer. In our approach we focus to optimize the latency of modern digital system by dividing the memory into groups. Following by activating, the fourth coming commands in advance in idle slots of different memory modules. The approach is called slag time management. In our algorithm effective distribution of memory into modules activating the later command in advance is followed by the advance dynamic buffers for saving the most frequently access arrays in it.The proposed technique of dividing the memory into modules utilizing the memory management idle slot management in use of advance of dynamic buffers has significantly approved the overall of latency ofRefference:
I. David Tawei Wang, “Modern DRAM Memory Systems: Performance Analysis and Scheduling Algorithm”, University of Maryland libraries,2005.
II. Fraboulet, G. Huard, A. Mignotte, “Loop Alignment for Memory Access Optimization”, 12th International Symposium on System Synthesis, 1999.
III. H. Shin, C. Kim, “A Simple Yet Effective Technique for Partitioning”, IEEE Transaction on Very Large Integration (VLSI) System, pp. 380- 386, 1993.
IV. J. I. Gomez, P. Marchal, S. Verdoorlaege, L. Pinuel, F. Catthoor, “Optimizing the Memory Bandwidth with Loop Morphing”, 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’04), 2004.
V. N. Kim, R. Peng, “A memory Allocation and Assignment Method Using Multi-Way Partitioning”, IEEE International SoC Conference, 2004.
VI. Prince, Betty, “High Performance Memories: New Architecture DRAMs and SRAMs — Evolution and Function”, 1st edition, 1996.
VII. P. R. Panda, N. D. Dutt and A. Nicolau, “Incorporating DRAM Access Modes into High-Level Synthesis”, IEEE Transaction on Computer-Aided Design, Vol. 17, pp. 96-106,1998.
VIII. P. R. Panda, N. D. Dutt, A. Nicolau, “Exploiting Off-Chip Memory Access Modes in High-Level Synthesis”, International Conference on Computer-Aided Design (ICCAD ’97), 1997.
IX. P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg, “Data and Memory Optimization Techniques for Embedded Systems”, ACM Transaction Design Automation Electron System, Vol. 6, no. 2, pp. 149-206, 2001.
X. P. R. Panda, “Memory Bank Customization and Assignment in Behavioral Synthesis”, ICCAD, 1999.
XI. P. Marchal, J. I. Gomez, F. Catthoor, “Optimizing the Memory Bandwidth with Loop Fusion”, IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS’04), 2004.
XII. S. Daud, H. shin, “Cycle Accurate Memory Delay Modeling for Off-Chip DRAMs”, System on Chip Conference, 2009.
XIII. S. J. E. Wilton and N. P. Jouppi, “CACTI: An Enhanced Cache Access and Cycle Time Model,” IEEE Journal of Solid state circuits, Vol. 31, pp. 667-688, 1996.
XIV. T. Kim, J. Kim, “Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory Access Optimization”, IEEE Transaction on Computer Aided Design of Integrated circuits and systems, vol. 26, no. 1, pp. 142-151, 2007.
XV. T. Wada, S. Rajan, and S. A. Przbylski, “An Analytical Access Time Model for On-Chip Cache Memories”, IEEE Journal of Solid State circuits, Vol. 27, pp. 1147-1156, 1992.