SQUARE OPERATION IMPLEMENTATION ON RECONFIGURABLE HARDWARE LOGIC TO ATTAIN HIGH SPEED, AREA OPTIMIZATION AND LOW POWER CONSUMPTION

Authors:

Avinash Patil,S. C. Patil,D. S. Bormane, Sushma Wadar,

DOI NO:

https://doi.org/10.26782/jmcms.spl.9/2020.05.00004

Keywords:

Vedic mathematics,Urdhva-Tiryagbhyam sutra,Dwandva Yog,Duplex Property,

Abstract

The contribution made by authors in the research work carried out on square operation is bought forward operated on a four and eight-bit number using duplex property of number based on Vedic mathematics. The conventional method of computing square of a number follows the polynomial multiplication of the same number to find the square. The said method requires the area and power consumption is not sufficiently optimized considering today’s low power application needs. The proposed method of computing the square of a number presented here is based on the Dwandva yog of Vedic mathematics which also called as duplex property of a number. The duplex method of calculating the square of number gives the online solution which can be easily calculated mentally and the efforts were to prove the same with the electronic circuit. The implementation of the square algorithm using polynomial multiplication and Vedic mathematics based duplex property for square operation is carried out with VHDL coding on the Xilinx Vivado 2015 ISE tool and the FPGA used is Artix7 device: 7a35tcpg236-1. The results were compared with 4-bit as well as 8-bit operation using both algorithms for a square operation are it is observed that the speed of operation is improved by 20 % whereas the hardware resources utilized were reduced by 66 %.

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