A NOVEL ARCHITECTURE FOR MULTI-BIT SHIFT AND ROTATE OPERATION

Authors:

Sushma Wadar,D S Bormane,S C Patil,Avinash Patil,

DOI NO:

https://doi.org/10.26782/jmcms.spl.9/2020.05.00003

Keywords:

Data reversal,Two’s complement,Shifter,Butterfly and Inverse butterfly,Shift/Rotate,Mask,

Abstract

In the available microprocessors and microcontrollers, the multi-bit operations are implemented with very less efficiency. Generally, these complex bit operations are emulated using programming logic. These bit manipulation operations are frequently required in the applications that are becoming very important. In this paper, we propose two new techniques which can directly support these bit operations in the form of shifter unit that can implement standard shifter operations in microprocessors and controllers. The design of the proposed shifter unit is based on the inverse butterfly circuit.[X] In this paper, we propose two techniques that have shift/rotate and mask circuits which enable the same circuit to perform all types of the standard shift and rotate operations found in some processors. The first technique is using Data reversal method and second using Two’s complement method. The design of Shifter-Permute functional unit is the important and critical task towars optimizing parameters such as speed, area and power consumption. Here we have implemented an 8-bit Shift-rotate functional unit for bit manipulation in the form of two approaches and have analyzed the circuits in terms of speed, area, and power consumption. Here the circuits are implemented and analyzed by using the most popular semi-custom design tool Vivado ISE 2015 and is synthesized by using Artix-7 FPGA and the same is reflected  in the mathematical model purposed for each circuit.

Refference:

I. Claudio Brunelli, ‘Design of Hardware Accelerators for Embedded Multimedia Applications’, 2009

II. Eduardo Jonathan Martínez Montes, Facultatd’Informàtica de Barcelona (FIB), “Design and implementation of a Multimedia Extension for a RISC Processor”,Master in Innovation and Research in Informatics (MIRI-HPC) ,2 July 2015.

III. GauravMitra, Beau Johnston, Alistair P. Rendell, and Eric McCreath, “Use of SIMD Vector Operations to Accelerate Application Code Performance on Low-Powered ARM and Intel Platforms”, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, 10.1109/IPDPSW.2013.207

IV. Mario Garrido, Member, Jesus Grajal and Oscar Gustafsson, “Optimum Circuits for Bit Reversal”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II: EXPRESS BRIEFS

V. Neil Burgess, “Assessment of Butterfly Network VLSI Shifter Circuit”, 978-1-4244-9721-8/10/ pp 92-96, Asilomar 2010 ©2010 IEEE

VI. Sabyasachi Das and Sunil P. Khatri, “A Timing-Driven Approach to Synthesize Fast Barrel Shifters”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 1,Pgs. 31-36, JANUARY 2008

VII. SushmaWadar, D S Bormane, S C Patil, AvinashPatil, ‘A Novel Approach to Perform Shift/Rotate and Bit Permutation Operation’, ICNTET, GRT Institute of Engineering and Technology, Tirutanni, Chennai.

VIII. SushmaWadar, D S Bormane, S C Patil, AvinashPatil, ‘A Novel Approach to Perform Shift/Rotate and Bit Permutation Operation’, ICNTET, GRT Institute of Engineering and Technology, Tirutanni, Chennai.

IX. White Paper, ‘Developing Embedded Applications with ARM® CortexTM-M1Processors in Actel IGLOO and Fusion FPGAs’, March 2009

X. Woo-KyeongJeong and Yong-Surk Lee, “A Universal Shifter with Packed Data Formats”, International Journal for Electronics and Communications, (AE¨U) 57 (2003) No. 6, Pgs. 420−422

XI. YedidyaHilewitz, Member, IEEE, and Ruby B. Lee, ‘A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulation’, IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 8, AUGUST 2009 pp 1036-1048

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