PERFORMANCE ANALYSISOF MOD2N -1 ADDERS AT SCHEMATIC AND RTL LEVEL USING CADENCE VIRTUOSO & ENCOUNTER TOOLS

Authors:

Gonuguntla Sailakshmi,Ashish Kumar Thakur,Sarada Musala,

DOI NO:

https://doi.org/10.26782/jmcms.2019.12.00053

Keywords:

Residue Number System,Forward Conversion,Reverse Conversion,Modular adder,Multiplexer,

Abstract

RNS has the ability toperform subtraction, addition independently with carryfree propagation. The structure of RNS requires two types of conversion: Forward Conversion and Reverse Conversion. To convert binary to residues, forward conversion is used whereas to convert residues to binary reverse conversion is used. Special moduli set and arbitrary moduli set are the two types of forward conversions. (2n-1) mod adder is one the important block used to get the special moduli set type of forward conversion. This paper consists of mod (2n-1) adders for the forward conversion technique and comparison of designs at both Schematic level and RTL level. The schematic level designs provides low power than RTL design whereas the delay is reduced in RTL than Schematic design. The designs have been simulated for RTL using NC Launch - Encounter tool standard 90nm Technology.The designs have been simulated using CMOS 90nm virtuoso tool in cadence for schematic designs.

Refference:

I. A.Omondi, B. PremKumar, “Residue Number System: Theory and
Implementation”, Imperial College Press 2007, ISBN 978-1-86094-866-4.
II. B.Cao, C.H.Chang, T.Srikanthan, “A Residue-to-Binary Converter for a New
Five-Moduli Set”, IEEE Trans. on Circuits and Systems-I: Regular Papers,
2007, Vol. 54, pp.1041-1049. doi:10.1109/TCSI.2007.890623.
III. Hamed Naseri and Somayeh Timarchi, “low-power and fast full adder by
exploring New XOR and XNOR gates”,IEEE Transactions on very large
scale integration systems,Aug. 2018, Vol. 26, no. 8, pp.1481-1493.
doi:10.1109/TVLSI.2018.2820999.

IV. N. S. Szabo, R.I. Tanaka, “Residue Arithmetic and its applications to
computer technology”, New York: Mc-Graw Hill, 1967.
V. R. Zimmermann,“Efficient VLSI implementation of modulo addition and
multiplication”, in proc. of IEEE Symposium on Computer Arithmetic, Apr.
1999, pp. 158-167. doi:10.1109/ARITH.1999.762841.
VI. Sharma, Neelam. “Analysis of Lactate Dehydrogenase & ATPase activity in
fish, Gambusia affinis at different period of exposureto chlorpyrifos.”
International Journal 4.1 (2014): 98-100.
VII. S. Akhter, R. Gaurav, S. Khan “Analysis and Design of Residue Number
System Based Building Blocks”, in proc. of 5th International Conference on
signal processing and Integrated Networks, 2018, pp.441-
445.doi:10.1109/SPIN.2018.8474204.
VIII. S. J. Piestrak, “A High speed Realization of a residue to binary number
system converter”, IEEE Transactions on Circuits and Systems-II: Analog
and Digital Signal Processing, 1995, Vol. 42, pp. 661-663.
doi:10.1109/82.471401.
IX. T. U. Narendra and et.al, “FPGA based efficient Architecture for conversion
of binary to residue number system”,inproc.of Information Technology,
Electronics and Mobile Communication conference, Oct 2017.
doi:10.1109/IEMCON.2017.8117238.

View Download