Authors:
SUDHAKAR ALLURI,DOI NO:
https://doi.org/10.26782/jmcms.2019.12.00023Keywords:
Low power,delay,area,FinFET SR Latch,FinFET NAND gate,DSP,VLSI,Abstract
In present days, low power Very Large Scale Integration (VLSI) circuit assumes a significant job in structuring effective vitality sparing electronic frameworks for rapid execution. In this, low power utilization one of the most significant criteria in different gadgets like cell phones, workstations, High-speed work stations, and so on. FinFETs area unit multi-door transistors that supply higher entry direct management is very little component advancements. They show higher and lower spillage contrasted with the Complementary metal oxide semiconductor planar. As appeared in Figure one, the door is created of a slim balance that associates the availability of the channel on to form the avenue. The avenue is middle between 2 facet entryways on 2 inverse sides. the weather of the door area unit calculable through the entry length, chemical compound thickness, balance dimension, and balance tallness. The activity of the FinFET semiconductor unit is basically similar because of the CMOS planate. In this paper, an SR Latch utilizing eight transistors has been proposed. The proposed SR Latch is planned to utilize the CADENCE EDA apparatus and re-enacted utilizing the Specter Virtuoso at FinFET 18 nm innovation. The proposed outcomes as far as power, area, and delay from table3, table4, table5, and table6.Refference:
I. Alshraiedeh and A. Kodi An adaptive routing algorithm to improve
lifetime reliability in NoCs architecture, IEEE International Symposium
on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
(DFT) (2016), pp. 127–130.
II. Amulya Boyina, K. Praveen Kumar “Active Coplanar Wave guide Fed
Switchable Multimode Antenna Design and Analysis” Journal Of
Mechanics Of Continua And Mathematical Sciences (JMCMS), Vol.-
14, No.-4, July-August (2019) pp 188-196.
III. Azizi, M. M. Khellah, V. K. De & F. N. Najm, Variations aware lowpower
design and block clustering with voltage scaling. IEEE Trans. Very
Large Scale Integr. Syst. 15, 746 (2007).
IV. Bahadori, M. Kamal, A. Afzali-Kusha & M. Pedram, A comparative study
on performance and reliability of 32-bit binary adders. Integr. VLSI J. 53,
54 (2016).
V. C. Catanzaro, K. Asanovic, D. A. Patterson, and K. A. Yelick, The
landscape of parallel computing research: A view from berkeley. EECS
Dep. Univ. Calif. Berkeley Tech. Rep. UCBEECS2006183 18, 19 (2006).
VI. Chen, A. Shafaei, Y. Wang, S. Chen, and M. Pedram, Maximizing the
performance of NoC-based MPSoCs under total power and power density
constraints, 17th International Symposium on Quality Electronic Design
(ISQED) (2016), pp. 49–56.
VII. Dousti, Q. Xie, X. Lin, Y. Wang, A. Shafaei, M. Ghasemi-Gol, and M.
Pedram, 5 nm FinFET standard cell library optimization and circuit
synthesis in near-and super-threshold voltage regimes, 2014 IEEE
Computer Society Annual Symposium on VLSI (2014), pp. 424–429.
VIII. G. Friedman, K. Xu, R. Patel and P. Raghavan, Exploratory design of onchip
power delivery for 14, 10, and 7 nm and beyond FinFET ICs.
Integration 61, 11 (2018).
IX. Hwang, Y. Li, S. Member, and T. Li, Process-variation effect, metal-gate
work-function fluctuation, and random-dopant fluctuation in emerging
CMOS technologies. IEEE Trans. Electron Devices 57, 437 (2010).
X. J. R. Ferreira, Analysis of many-core CPUs simulators. Tech. Rep.,
Instituto Superior Tecnico, Universidade de Lisboa, pp. 1–10.
XI. K Satish Reddy a, K Praveen Kumar, Habibulla Khan, Harswaroop Vaish
“Measuring the surface properties of a Novel 3-D Artificial Magnetic
Material” 2nd International Conference on Nanomaterials and
Technologies (CNT 2014), Elsevier Procedia material Science.
XII. K.Praveen Kumar, “Design of 3D EBG for L band Applications” IEEE
International conference on communication technology ICCT-April-2015.
Noor Ul Islam University Tamilnadu.
XIII. K.Praveen Kumar, “Effect of 2DEBG structure on Monopole Antenna
Radiation and Analysis of It’s characteristics” IEEE International
conference on communication technology ICCT-April-2015. Noor Ul
Islam University Tamilnadu.
XIV. K.Praveen Kumar, “Mutual Coupling Reduction between antenna
elements using 3DEBG” IEEE International conference on
communication technology ICCT-April-2015. Noor Ul Islam University
Tamilnadu.
XV. K.Praveen Kumar, “The surface properties of TMMD-HIS material; A
measurement” IEEE International conference on communication
technology ICCT-April-2015. Noor Ul Islam University Tamilnadu.
XVI. K.Praveen Kumar, “Active Switchable Band-Notched UWB Patch
Antenna”, International Journal of Innovative Technology and Exploring
Engineering (IJITEE), Volume-8 Issue-8 June, 2019.
XVII. K.Praveen Kumar, “Circularly Polarization of Edge-Fed Square Patch
Antenna using Truncated Technique for WLAN Applications”,
International Journal of Innovative Technology and Exploring
Engineering (IJITEE), Volume-8 Issue-8 June, 2019.
XVIII. K.Praveen Kumar, “Triple Band Edge Feed Patch Antenna; Design and
Analysis”, International Journal of Innovative Technology and Exploring
Engineering (IJITEE), Volume-8 Issue-8 June, 2019.
XIX. K.Praveen Kumar, Dr Habibulla Khan ” Surface wave suppression band,
In phase reflection band and High Impedance region of 3DEBG
Characterization” International journal of applied engineering research
(IJAER), Vol 10, No 11, 2015.
XX. K.Praveen Kumar, Dr Habibulla Khan ” The surface properties of
TMMD-HIS material; a measurement” IEEE International conferance on
electrical, electronics, signals, communication & optimization EESCO –
January 2015.
XXI. K.Praveen Kumar, Dr. Habibulla Khan ” Active progressive stacked
electromagnetic band gap structure (APSEBG) structure design for low
profile steerable antenna applications” International Conference on
Contemporary engineering and technology 2018 (ICCET-2018) March 10
– 11, 2018. Prince Shri Venkateshwara Padmavathy Engineering College,
Chennai.
XXII. K.Praveen Kumar, Dr. Habibulla Khan “Active PSEBG structure design
for low profile steerable antenna applications” Journal of advanced
research in dynamical and control systems, Vol-10, Special issue-03,
2018.
XXIII. K.Praveen Kumar, Dr. Habibulla Khan “Optimization of EBG structure
for mutual coupling reduction in antenna arrays; a comparitive study”
International Journal of engineering and technology, Vol-7, No-3.6,
Special issue-06, 2018.
XXIV. K.Praveen Kumar, Dr. Habibulla Khan “Optimization of EBG structures
for Mutual coupling reduction in antenna arrays; A comparative study”
International Conference on Contemporary engineering and technology
2018 (ICCET-2018) March 10 – 11, 2018. Prince Shri Venkateshwara
Padmavathy Engineering College, Chennai.
XXV. K.Praveen Kumar, Dr. Habibulla Khan, “Design and characterization of
Optimized stacked electromagnetic band gap ground plane for low profile
patch antennas” International journal of pure and applied mathematics,
Vol 118, No. 20, 2018, 4765-4776.
XXVI. K.Praveen Kumar, Kumaraswamy Gajula “Fractal Array antenna Design
for C-Band Applications”, International Journal of Innovative Technology
and Exploring Engineering (IJITEE), Volume-8 Issue-8 June, 2019.
XXVII. Kumaraswami Gajula, Amulya Boyina, K. Praveen Kumar “Active Quad
band Antenna Design for Wireless Medical and Satellite Communication
Applications” Journal Of Mechanics Of Continua And Mathematical
Sciences (JMCMS), Vol.-14, No.-4, July-August (2019) pp 239-252.
XXVIII. Lim, H. Kim, H. Oh, and S. Kang, Dynamic voltage frequency scalingaware
refresh management for 3D DRAM over processor architecture.
Electron. Lett. 53, 910 (2017).
XXIX. Liu, R. Kim, P. Wettin, R. Marculescu, D. Marculescu, and P. P. Pande,
Energy-efficient VFI-partitioned multicore design using wireless NoC
architectures, Proceedings of the 2014 International Conference on
Compilers, Architecture and Synthesis for Embedded Systems-CASES
’14 (2014), pp. 1–9.
XXX. M. E. Salehi and H. Nejatollahi Voltage scaling & dark silicon in
symmetric multicore processors. J. Supercomput. 71, 3958 (2015).
XXXI. N. S. Kim, S. K. Khatamifard, M. Resch & U. R. Karpuzcu, VARIUS-TC:
A modular architecture-level model of parametric variation for thinchannel
switches. Proc. 34th IEEE Int. Conf. Comput. Des. ICCD 2016
(2016), pp.654–661.
XXXII. Navi, A. Arasteh, M. Hossein Moaiyeri, M. Taheri, and N. Bagherzadeh,
An energy and area efficient 4:2 compressor based on FinFETs. Integr.
VLSI J. 60, 224 (2018).
XXXIII. Nejatollahi, M. Ersali, and S. Nasab, Reliability-aware voltage scaling of
multicore processors in dark silicon era. Big Data and HPC: Advances in
Parallel Computing Ecosystem and Convergence (2018), Vol. 33, pp.242–
262.
XXXIV. S. S. Majzoub, R. A. Saleh, S. J. E. Wilton & R. K. Ward, Energy
optimization for many-core platforms: Communication and PVT aware
voltage-island formation and voltage selection algorithm. IEEE Trans.
Comput. Des. Integr. Circuits Syst. 29, 816 (2010).
XXXV. Singh, B. S. Reniwal, V. Vijayvargiya, V. Sharma & S. K. Vishvakarma,
Ultra low power-high stability, positive feedback controlled (PFC) 10T
SRAM cell for look up table (LUT) design. Integration 62, 1 (2018).
XXXVI. Stamelakos, S. Xydis, G. Palermo, and C. Silvano, Workload- and
process-variation aware voltage/frequency tuning for energy efficient
performance sustainability of NTC manycores. Integration (2018), In
Press.
XXXVII. Stillmaker and B. Baas, Scaling equations for the accurate prediction of
CMOS device performance from 180 nm to 7 nm. Integration 58, 74
(2017).
XXXVIII. T. Cui, J. Li, Y. Wang, S. Nazarian & M. Pedram, “An exploration of
applying gate-length-biasing techniques to deeply-scaled FinFETs
operating in multiple voltage regimes”, IEEE Transi. Emer. Top. Compu.
six, 172 (2018).
XXXIX. Uddin, R. Poss, and C. Jesshope, Cache-based high-level simulation of
microthreaded many-core architectures. J. Syst. Archit. 60, 529 (2014).
XL. Venkateswar Rao, Praveen Kumar Kancherla, Sunita Panda “Multiband
slotted Elliptical printed Antenna Design and Analysis” Journal Of
Mechanics Of Continua And Mathematical Sciences (JMCMS), Vol.-14,
No.-4, July-August (2019) pp 378-386.
XLI. W. Jose, A. R. Silva, H. Neto, & M. Vestias, Modeling and simulation of
a many-core architecture using systemC. Conf. Electron. Telecommun.
Comput. 17, 146 (2014).
XLII. X. Lin, Y. Wang, & M. Pedram, Joint sizing and adaptive independent
gate control for FinFET circuits operating in multiple voltage regimes
using the logical effort method, 2013 IEEE/ACM International
Conference on Computer-Aided Design (ICCAD), (2013), pp. 444–449.
XLIII. Z. Hao, S. X.-D. Tan, and G. Shi, Statistical full-chip total power
estimation considering spatially correlated process variations. Integr.
VLSI J. 46, 80 (2013).