Authors:
B. Karthik,M. Jasmin,S. Arulselvi,M. Sriram,DOI NO:
https://doi.org/10.26782/jmcms.spl.2019.08.00055Keywords:
MOS,High Speed VLSI,Interconnect Scaling,Abstract
Scaling the MOS interconnection line widths, improves the layout density, but the intrinsic propagation delays along maximum length lines are becoming significant and that the coupling between adjacent lines due to ever shrinking separation is also increasing to a noticeable level. In this paper we show the effects of the classical scaling on the effective delay and the coupling capacitance.Refference:
I. BaccaraniG., M. R. Wordeman, and R. H. Dennard, “Generalized scaling theory
and its application to a 1/4 micron MOSFET design,” IEEE Trans. Electron
Devices, vol. ED-3 1, pp. 452462, Apr. 1984
II. BohrM.T., Semiconductor International, Vol. 18, No.6. (1995) p.75
III. Cottrell P. E. and E. M. Burtula, “VLSI wiring capacitance,” IBM Journal of
Research and Development, vol. 29, pp. 277-287, May 1985.
IV. DennardR. H., F. H. Gaensslen, H. N. Yu, N. L. Rideout, E. Bassous, and A. R.
LeBlanc, “Design of ion-implanted MOSFET’s with very small physical
dimensions,” IEEE J. Solid State Circuits, vol. SC-9, pp. 256-268, October 1974.
V. DonathW. E., “Placement and average interconnect lengths of computer logic,”
IEEE Trans. Circuits and Systems, vol. CAS-26, pp. 272-277, April 1979.
VI. ElmoreW. C., “The transient response of damped linear networks with particular
regard to wide-band amplifiers,” Journal of Applied Physics, vol. 19, pp. 55-63,
January 1948.
VII. FerryD. K., “Interconnection lengths and VLSI,” IEEE Circuits and Devices
Magazine, vol. 1, pp. 39-42, July 1985
VIII. Steven Paul McCormick, “Modeling and Simulation of VLSI Interconnections
with Moments”. PhD thesis. Massachusetts Institute of Technology Cambridge,
MA 02139 USA.