Authors:
S. Arulselvi,B. Karthik,M. Jasmin,Balaji S,DOI NO:
https://doi.org/10.26782/jmcms.spl.2019.08.00051Keywords:
Parallel processing,Pipelining,Matrix multiplier,Clock timing,design area,Abstract
Concurrent data processing is used is used to rise the computational speed of computer system in parallel processing. This is implemented by pipeline processing. In this article we offered design of a Pipelined Matrix Multiplier and its results is stored in matrix. We present design and stimulate a functional Pipelined Matrix Multiplier Unit. By which we can learn about the working of Pipelined Matrix Multiplier and how pipelining works. We also get the knowledge of clock timing and learn to make a timing critical design. In this Pipelined Matrix Multiplier Unit design we use design compiler, which is a module of Synopsys tools that uses lsi_10k library and BCCOM method to synthesis the design and simulate the design through VCS compiler.Refference:
I. AlmasharyB., S. M. Qasim, S. A. Alshebeili, and W. Almasry,
“Realization of Linear Back-Projection Algorithm for Capacitance
Tomography Using FPGA”, Proc. of 4th World Congress on Industrial
Process Tomography, Aizu, Japan, pp. 87-93, Sept. 2005.
II. Fisher J.A. “Trace scheduling:a technique for global Micro code Compation.
”IEEE Trans.on Computers,C(30)7:478,August,2005.
III. FoleyJ. D., A. van Dam, S. K. Feiner, and J. F. Hughes, “Computer Graphics,
Principles and Practice”, AddisonWesley, second edition, 1996.
IV. JangJ., S. Choi, and V. K. Prasanna, “Area and Time Efficient
Implementation of MatrixMultiplication OnFPGA”, InProceedings of the
IEEE International Conference on Field-Programmable Technology, 2002.
V. Jianwen L.and J.C.Chuen,“Partially Reconfiguarble Matrix for Area and
Time Efficiency on FPGAs”, In proc. of EuromicroSymp on Digital System
Design, pp. 244-248,2004
VI. Kittitornkun S. and Y. H. Hu, “Mapping Deep Nested Do-loop DSP
Algorithms to Large Scale FPGA Array Structures,” IEEE Trans. on
VLSI Systems, Vol. 11, No. 2, pp. 208–217, April 2003.
VII. Mak W. K. and L. Hao, “Placement for modern FPGAs,” in Proc. of
Emerging Information Technology Conference, pp. 1-4, 2005.
VIII. ManohararajahV., S. D. Brown, and Z. G. Vranesic, “Heuristics for area
minimization in LUT-based FPGA technology mapping,” IEEE Trans. on
Computer Aided Design of Integrated Circuits and Systems, Vol. 25, No. 11,
pp. 2331-2340, 2006
IX. McCanny J. V. and J. C. White, “VLSI Technology and Design”, Academic
Press, 1987.
X. ScrofanoR., J.-W. Jang, and V. K. Prasanna, “Energy-Efficient discrete
cosine transform on FPGAs,” in Proc. Engineering of Reconfigurable
Systems and Algorithms (ERSA), 2003, pp. 215–221
XI. SrivastavaN., J. L. Trahan, R. Vaidyanathan, and S. Rai, “Adaptive image
filtering using run-time reconfiguration,” in Proc. Reconfigurable
Architectures Workshop (RAW), 2003.